1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more specifically, to a method for manufacturing a flash memory device which can improve the interfacial characteristics of a floating gate and a dielectric layer.
2. Discussion of Related Art
Recently, in implementing DATA Flash devices, an isolation layer is formed by means of a self-aligned shallow trench isolation (SA-STI) process. The SA-STI process can be explained in short as follows. A tunnel oxide layer, a first polysilicon layer and a pad nitride layer are sequentially formed. The pad nitride layer, the first polysilicon layer and the tunnel oxide layer in the isolation region are then etched and etch is performed up to a semiconductor substrate, thereby forming a trench. The trench is then buried with an insulating material to form an isolation layer of a STI structure.
Thereafter, a second polysilicon layer into which an impurity is doped is formed on the entire structure. A portion of the second polysilicon layer on the isolation layer is etched. An ONO dielectric layer, a third polysilicon layer and a silicide layer are sequentially formed on the entire structure including the second polysilicon layer. A patterning process is then performed by means of an etch process using a control gate mask. A floating gate having the first and second polysilicon layers is thus formed and a control gate having the third polysilicon layer is formed, thereby completing a flash memory cell.
In the above, the ONO dielectric layer has a stack structure of a first oxide layer/a nitride layer/a second oxide layer, wherein the oxide layer is formed using DCS-HTO. At this time, in the process of loading a semiconductor substrate into a boat of a high temperature in order to form the first oxide layer, an irregular oxide layer is formed at the interface of the second polysilicon layer. Meanwhile, after the ONO dielectric layer is formed, a high-temperature annealing process is implemented in a wet oxidization mode at a temperature of 750° C. or more in order to remove the causes of the leakage current such as the density and pin-hole of the dielectric layer. The second polysilicon layer is oxidized at the interface of the first oxide layer and the second polysilicon layer due to the annealing process of the high temperature, making the dielectric layer irregular.
Furthermore, in order to form the control gate, an etch process is carried out after the third polysilicon layer is formed. In order to mitigate the etch stress generated at the sidewall of the third polysilicon layer exposed by the etch process, an annealing process is performed as a subsequent process at a high temperature of 800° C. In this case, in order to increase the effect of the annealing process, the sidewall of the third polysilicon layer is oxidized in a predetermined thickness. In this process, the oxide layer is formed at the interface of the oxide layer and the polysilicon layer. For this reason, there occurs a difference between the effective oxide layer thickness (Teff) of the dielectric layer inside the gate and the effective oxide layer thickness of the gate sidewall, thus making the effective oxide layer thickness irregular. Moreover, the effective oxide layer thickness is increased since the dielectric layer becomes thick, which reduces capacitance. Furthermore, such irregular oxidization acts as the cause of the leakage current and also lowers the breakdown voltage, which adversely affects the operation of the cell.